An EL device is a luminescent device that emits light when an electric current is injected and a current setting type light emission control system can be used for a luminescent device.
FIG. 11 of the accompanying drawings schematically illustrates the configuration of a current setting type pixel circuit including an EL device. The part other than the EL device in FIG. 11 is the pixel circuit. In FIG. 11, P11 and P12 denote scan signals. On the other hand, current data “Idata” is input as an information signal.
The anode (A in FIG. 11) of the EL device is connected to the drain terminal of thin film transistor (TFT) MP4, while the cathode (K in FIG. 11) of the EL device is connected to the grounding potential GND. MP1, MP2 and MP4 are p-type thin film transistors (PMOS transistors) and MP3 is an n-type thin film transistor (NMOS transistor). Now, the operation of the pixel circuit will be described below.
When current data “Idata” is input, a LOW level signal is input to a scanning line 104 as a scan signal P11, while a HIGH level signal is input to a scanning line 105 as a scan signal P12. At this time, the transistors MP2 and MP3 are brought into an ON state, while the transistor MP4 is brought into an OFF state. Since the transistor MP4 is not in a conducting state, no electric current flows to the EL device. A voltage that corresponds to the electric current driving capability of the transistor MP1 is produced by the current data “Idata” at capacity C arranged between the gate terminal of the transistor MP1 and the power supply voltage “Vcc”. In this way, the electric current that is made to flow to the EL device is retained as the potential of the gate of the transistor MP1.
When supplying an electric current to the EL device, a HIGH level signal is input as a scan signal P11, while a LOW level signal is input as a scan signal P12. At this time, the transistor MP4 is brought into an ON state, while the transistors MP2 and MP3 are brought into an OFF state. Since the transistor MP4 is in conducting state, an electric current that corresponds to the electric current driving capability of the transistor MP1 is supplied to the EL device by the voltage produced at the capacity C and the EL device emits light with a luminescence intensity that corresponds to the supplied electric current.
FIG. 12 of the accompanying drawings illustrates the circuit configuration of an EL display apparatus formed by arranging pixel circuits and EL devices respectively in the row direction and in the column direction to form a two-dimensional matrix.
R(red)/G(green)/B(blue) input video signal 210 (to be referred to simply as an input video signal hereinafter) is input to a series of column-current generating circuits 201, the number of which is three times as many as the horizontal pixels of the EL panel. Subsequently, horizontal control signal 211a is input to an input circuit 206 and horizontal control signal 211 is output from the input circuit 206 and input to a horizontal shift register 203.
Auxiliary column control signal 213a is input to an input circuit 208 and auxiliary column control signal 213 is output from the input circuit 208 and input to gate circuits 204 and 216.
Horizontal sampling signal group 217 outputs to the output terminals that correspond to the respective columns of the horizontal shift register 203 is input to a gate circuit 215 where control signal 211 output from the gate circuit 216 is input. The horizontal sampling signal group 218 transformed by the gate circuit 215 is input to the column-current generating circuit 201. The column-current generating circuit 201 is controlled by a control signal 219 output from the gate circuit 204.
Vertical control signal 212a is input to an input circuit 207 and a vertical control signal 212 is output from the input circuit 207 and input to a vertical shift register 205, while scanning signals are input to row control lines 304.
A data signal from the column-current generating circuit 201 is input to each pixel circuit by way of a data line 302. In FIG. 12, a pixel region 209 is formed by pixel circuits and EL devices.
FIG. 13 of the accompanying drawings schematically illustrates an exemplar circuit configuration of the column-current generating circuit 201. FIG. 14 of the accompanying drawings is a timing chart of the operation of the column-current generating circuit 201. The circuit is disclosed in U.S. Pat. No. 7,126,565. Since the configuration and the operation of the circuit are disclosed in detail in the above-cited patent document, they will be described here only summarily.
The column-current generating circuits 201 transform video signal “video” as an input signal into current signal “Idata” and outputs the current signal “Idata”.
Video signal video is input from the signal input terminals, which are the source of the transistor M1 and the source of the transistor M7. Horizontal sampling signals “SPa” and “SPb” are input respectively to the gates of the transistor M1 and the transistor M7.
The drain of the transistor M1 is connected to one of the terminals of the capacity C1. The other terminal of the capacity C1 is connected to the drain of the transistor M2, the gate of the transistor M3 and one of the terminals of capacity C2. The drain of the transistor M3 and the other terminal of the capacity C2 are connected to GND. Control signal “P1” is input to the gate of the transistor M2.
The source of the transistor M2 and the source of the transistor M3 are connected to the drain of the transistor M4 and that of the transistor M6. Control signals “P2” and “P3” are input respectively to the gate of the transistor M4 and the gate of the transistor M6.
Current signal “Idata” is output from the source of the transistor M6 that is a signal output terminal to the data line. The source of the transistor M4 is connected to the power supply “Vcc” by way of the transistor M5.
While the circuit configuration downstream to the drain of the transistor M1 is described above, the circuit configuration downstream to the drain of the transistor M7 has similar configuration. In other words, the capacities C1 and C2 and the transistors M2 through M6 correspond respectively to capacities C3 and C4 and transistors M8 through M12. The circuit of the transistors M1 through M6 and the capacities C1 and C2 may be used for writing on the odd number pixel rows, whereas the circuit of the transistors M7 through M12 and the capacities C3 and C4 may be used for writing on the even number pixel rows.
To improve the response speed of a thin film transistor (TFT), polysilicon (p-Si) that shows an electron mobility higher than amorphous silicon (a-Si) is desirably used. To form a polysilicon layer on an insulating substrate such as a glass substrate, generally, the substrate is irradiated with a laser beam such as an excimer laser beam in order to heat and melt a-Si on the substrate and recrystallize a-Si into p-Si.
U.S. Pat. No. 6,781,153 discloses a technique of forming transistors of the pixel circuit of an organic EL display apparatus by connecting a plurality of TFTs in parallel in order to suppress the dispersion of characteristics attributable to laser anneal using a laser beam.
When transistors having a non-single-crystal semiconductor film such as polysilicon film as an active layer are adopted in a column-current generating circuit as illustrated in FIG. 13, the dispersion of crystal grain size gives rise to dispersion of the electric characteristics of the transistors including the amplification factor. Then, as a result, the electric current supplied by the column-current generating circuit shows dispersion, which by turn may produce non-uniformity of display such as vertical streaks appearing in the image being displayed by the EL devices.